A test is performed to verify the performance and reliability of semiconductor memory devices and to improve the throughput. Among those things, a burn-in test is used to test reliability of the semiconductor memory devices. The burn-in test includes applying a stress to semiconductor memory devices for a long time under a high voltage and a high temperature to find defective memory devices. In particular, there is an increasing demand for a die of a wafer state rather than a package state. Recently, there is an increasing need for the package shape such as MCM or CSP shape. The wafer burn-in test becomes thus increasing important. Further, the wafer burn-in test can reduce the time and cost of the burn-in test performed in a package level.
Referring now to FIG. 1, a construction of a conventional wafer burn-in test mode circuit is described. A command decoder 101 receives various signals necessary for semiconductor memory devices including a row address select bar signal RAS/, a column address select bar signal CAS/, a write enable bar signal WE/, a chip select bar signal CS/, a clock enable signal CKE and a clock signal CLK to generate various commands necessary to drive the semiconductor memory devices. For example, the command decoder 101 generates a mode register set command signal MRS and a precharge signal Precharge All.
An address latch 102 receives and latches a plurality of address signals A0 through An depending on a command signal from the command decoder 101. The mode register 103 stores an address signal for a normal operation from the address latch 102 depending on the mode register set command signal MRS from the command decoder 101. A normal test mode register 104 stores an address signal for a normal test from the address latch 103 depending on the mode register set command signal MRS from the command decoder 101.
A test mode entry circuit 105 receives the mode register set command signal MRS from the command decoder 101 and a corresponding address signal from the address latch 102 as inputs to generate a test mode entry signal TM—Entry for performing the normal test. A wafer burn-in test mode register 106 stores an address for a wafer burn-in test from the address latch 103 depending on the mode register set command signal MRS from the command decoder 101. A wafer burn-in test mode entry circuit 107 receives the mode register set command signal MRS from the command decoder 101 and a corresponding address signal from the address latch 102 as inputs to generate a wafer burn-in test mode entry signal WBI—Entry for performing the wafer burn-in test.
A mode register decoder 108 decodes an output signal from the mode register 103 depending on the mode register set signal MRS from the command decoder 101 to output a control signal for a normal operation of the semiconductor memory devices. A normal test mode register decoder 109 decodes an output signal from the normal test mode register 104 depending on the mode register set signal MRS from the command decoder 101 and the test mode entry signal TM—Entry from the test mode entry circuit 105 to output normal test signals TM0–TM131.
A wafer burn-in test mode register decoder 110 decodes an output signal from the wafer burn-in test mode register 106 depending on the mode register set signal MRS from the command decoder 101 and the wafer burn-in test mode entry signal WBI—Entry from the wafer burn-in test mode entry circuit 107 to output wafer burn-in test signals WBI—TM0–WBI—TM15.
The conventional wafer burn-in test mode circuit constructed above, however, is almost similar to a normal test mode circuit or is included in the normal test mode circuit if there is a few item. The wafer burn-in test mode circuit requires more than one address signals to distinguish the normal test mode and the wafer burn-in test mode. Thus, four address signals are required to test more than five items. In view of a characteristic of the burn-in apparatus, however, the number of a channel available is only 13 through 18. Thus, if the number of a wafer burn-in test item is increased, there is a problem that the number of a necessary channel is short. Further, upon a layout, the number of a global line necessary in routing between the wafer burn-in test mode circuit and the address latch is increased.
Therefore, there is a need to provide a wafer burn-in test mode circuit capable of overcoming the limits of a burn-in apparatus having a small number of a channel to support various test items with only a single address signal in a wafer burn-in test, and a need for a wafer burn-in test mode circuit capable of reducing the number of a global line upon a layout.